Programmable integrated circuits are a type of integrated circuit that can be configured by a user to implement custom logic functions. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. When the design process is complete, the CAD tools generate configuration data. The configuration data is loaded into a programmable integrated circuit to configure the device to perform desired logic functions.
In a typical system, a programmable integrated circuit, memory devices, and other electronic components are mounted on a printed circuit board. The programmable integrated circuit includes memory interface circuitry that is used to relay data back and forth between the programmable integrated circuit and the memory devices (i.e., the memory interface circuitry is used to read data from and write data into the memory devices).
In general, the memory interface circuitry can be implemented as either an “in-order” or an “out-of-order” memory controller. In-order memory controllers process memory access requests in order and offer determinism on memory scheduling but often lack scheduling efficiency in terms of memory bandwidth utilization. Out-of-order memory controllers can process access requests out of order and can offer improved memory bandwidth utilization but the scheduling is non-deterministic.
Conventional memory interface circuitry on a programmable integrated circuit typically only addresses memory scheduling efficiency in a single usage domain (i.e., the memory interface can either be “hardened” for high performance and low power applications or can be “soft” to support slower or lower cost applications). Hardened/fixed application-specific memory interface solutions offer higher operating frequencies but pose challenges when scaling across different memory protocols and topologies. On the other hand, soft/programmable solutions offer more flexibility in supporting different memory protocols and topologies but are limited in terms of the scheduling efficiency and performance.